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If we were thinking the Cavium and Hisilicon SoCs being such a difficult milestone to overcome, sporting respectively 48 and 32 integrated cores, we'll have to retrace our steps due to the work of the Israeli EZchip chipmaker, working on the new Tile-MX100 100-core ARM Cortex-A53 SoC.

 

 

This SoC is particularly dedicated to Data Centers and Cloud Servers (same use of HISilicon and AMD ARM SoCs) where the raw power does not particularly matter compared to an excellent performance / consumption ratio; the same EZchip writes: “EZchip’s TILE-Mx is specifically designed to address these challenges through a highly parallel and optimized architecture leveraging proven hardware accelerators from EZchip’s market leading network processors, and Tilera’s many-core processors with market leading performance-per-watt and linear scaling” (Tilera, specialized in the production of embedded multi-core processors, was acquired this year by EZchip).

Of course this is an extreme SoC, dedicated to companies and organisations that require a high computing power in a small space and, to meet the customers' needs for a smaller solution, EZchip is even studying 32 and 64 cores versions (respectively named Tile-MX32 and MX64).

Specifically talking about the areas of use of these products, EZchip is expecting in the near future a significant increase of the demand for high-density servers able to operate in high virtualized environments: “Multicore CPUs represent a fast growing market – 38% growth from 2012 to 2013 according to the Linley Group 2014 Guide to Multicore Processors – and are used in a wide variety of systems, particularly in network appliances, white boxes, server blades and NFV servers to perform load balancing, security, network monitoring, SDN & NFV, virtualization, application recognition and video processing for data center, cloud, enterprise and carrier networks”.

Currently we do not know the detailed specifications of these Soc, as their sale is expected to commence from December 2016, but we assume a high integration of I / O CTRLs and Ethernet connections, along the steps of AMD's Seattle (which is bigger).

From the press release: "In addition, the chip boasts an optimized memory architecture with extremely high bandwidth to both the internal and external memories, and numerous interfaces for 1GE, 10GbE, 25GbE, 40GbE, 50GbE and 100-Gigabit Ethernet as well as PCI-Express".

It may happen that, during these months, the idea of going on with an updated Cortex-A72 version could arise.

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Gian Maria Forni
Autore: Gian Maria Forni
Esperto in:
Esperto di mercati e CPU
Sebbene sia laureato in Lettere e Filosofia, indirizzo Storia Contemporanea, e scriva per quotidiani e riviste di tale settore, ha sempre avuto la passione per l'informatica ed ha collaborato quale moderatore in importanti forum del settore
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