Official Global foundries marketing slides gives us some interesting quantitative informations on differences between new 14nm process and old 28nm process. It also states what are the current features that can be used in a 14nm design, in terms of library density and Vt options. Before now we could only guess about it. This is not a technical deep paper, but it's enough to draw some conclusions.
First of all, the various options cover both low power design, including ultra low power, and high performance design, despite the process is known as low power. That name is well earned because, as we will see, the new process has significant low power than the old 28nm BULK. But the process is capable also of high performance, with acceptable power consumption, so it's suitable also for high performance CPUs, just like Ryzen.
The document advertise also a full stack of design tools and packaging options, that depict an all-in-one available to system developers. We could expect that the performance and clock depicted in the slides are relative to the IP libraries provided by GloFo, but we could expect that AMD has it's own proprietary libraries, that have better performance or better power consumption. So we could expect that those figures are the minimum possible for Ryzen performance.
The document continues with a brief explaination of the 14nm FinFET process. Then some numbers are given relative to the 28nm process. 60% power reduction (at iso frequency) is common to both low and high power designs. The area reduction is higher in high power design, probabily because they can be done also with 9T libraries, that is a relatively high density library. More on later. Finally the performance (namely frequency) gain is given only for low power design, 80%, probabily because with high power design the increase is not so spectacular. The frequency information is probabily referring to Jaguar and Ryzen processors.
The second page goes more in detail with the features of the process:
Let's analyze the graph. Here we see the low Vcore range of the process, ranging from 0.5 to 0.9V. For comparison, the 15W APU FX9800P has 1.05V default Vcore, (source: http://valid.x86.fr/yajvy9 ) not so too far away in this graph. Here we see the proof of the first page statements. We can also see that on low power design, the 7.5T curve (green) is even better than 9T curve (red) on low clock CPUs. This can be expected, since also on 28nm HDL libraries are higher density and low clock optimized. In other words, HDL libraries are more power hungry at very high frequencies, but are denser and less power hungry at low clocks.
AMD latest APUs are made with high density libraries and despite that, they managed to hit 4.1/4.3GHz clocks on 95W quad core APU (A10-7890K). We can draw some conclusions, based on this graph.
Low power APUs: 60% power reduction means that we can have a 15W APU with double the cores and the SP than on 28nm. We can have 4m/8c Excavator and 1024SPs at the same clock. But newer architectures are more power efficient (Ryzen and Vega), so a 15W APU could have 4 Ryzen cores in the 3GHz+ range and 1024 SPs in the 1GHz range, according to this graph.
Talking of high core count servers, we can expect that 8 Zen core at 3GHz can draw just 30-40W. This means that 32c 180W Naples could have more than 3GHz base clock. Finally, this graph let us estimate also the final Ryzen clocks: 4x2.7GHz Ryzen cores should draw at most 15W. So 8x2.7GHz Ryzen core should draw at most 30W. Assuming cubic scaling with frequency for power drawn, we have that at 95W we can have (95/30)^(1/3)=1.47 times 2.7GHz, that are about 4GHz, just similar to the scaling of the 15W FX9800P versus the 95W A10-7890K.
These estimations are only ballpark, but we are confident that are quite realistic.
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