Important differences between S.I. and C.I. GPUs

•Multi queue compute
Lets multiple user-level queues of compute workloads be bound to the device and processed simultaneous. Hardware supports up to eight compute pipelines with up to eight queues bound to each pipeline.
•System unified addressing
Allows GPU access to process coherent address space.
•Device unified addressing
Lets a kernel view LDS and video memory as a single addressable memory. It also adds shader instructions, which provide access to “flat” memory space.
•Memory address watch
Lets a shader determine if a region of memory has been accessed.
•Conditional debug
Adds the ability to execute or skip a section of code based on state bits under control of debugger software. This feature adds two bits of state to each wavefront; these bits are initialized by the state register values set by the debugger, and they can be used in conditional branch instructions to skip or execute debug-only code in the kernel.
•Support for unaligned memory accesses
•Detection and reporting of violations in memory accesses

Summary of kernel instruction change from S.I. to C.I.


New instruction formats:
•FLAT

New instructions:
•FLAT_* (entire family of operations)
•S_CBRANCH_CDBGUSER
•S_CBRANCH_CDBGSYS
•S_CBRANCH_CDBGSYS_OR_USER
•S_CBRANCH_CDBGSYS_AND_USER
•S_DCACHE_INV_VOL
•V_TRUNC_F64
•V_CEIL_F64
•V_FLOOR_F64
•V_RNDNE_F64

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•V_QSAD_PK_U16_U8
•V_MQSAD_U16_U8
•V_MQSAD_U32_U8
•V_MAD_U64_U32
•V_MAD_I64_I32
•V_EXP_LEGACY_F32
•V_LOG_LEGACY_F32
•DS_NOP
•DS_GWS_SEMA_RELEASE_ALL
•DS_WRAP_RTN_B32
•DS_CNDXCHG32_RTN_B64
•DS_WRITE_B96
•DS_WRITE_B128
•DS_CONDXCHG32_RTN_B128
•DS_READ_B96
•DS_READ_B128
•BUFFER_LOAD_DWORDX3
•BUFFER_STORE_DWORDX3

Removed instructions:
•V_QSAD_U8
•V_MQSAD_U8
•BUFFER_ATOMIC_RSUB, _X2
•IMAGE_ATOMIC_RSUB, _X2